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1 wideband, low-power, ultra-high dynamic range differential amplifier ISL55210 the ISL55210 is a very wide band, fully differential amplifier (fda) intended for high dyna mic range adc input interface applications. this voltage feedback fda design includes an independent output common mode voltage control. intended for very high dynamic range adc interface applications, at the lowest quiescent power (115mw), the ISL55210 offers a 4.0ghz gain bandwidth product with a very low input noise of 0.85nv/ (hz). in a balanced differential i/o configuration, with 2v p-p output into a 200 ? load configured for a gain of 15db, the im3 terms are <-100dbc through 110mhz. with a minimum operating gain of 2v/v (6db), the ISL55210 supports a wide range of higher gains with minimal bw or sfdr degradation. its ultra high differential slew rate of 5,600v/s ensures clean large signal sfdr performance or a fast settling step response. the ISL55210 requires only a single 3.3v (max 4.2v) power supply with 35ma typical quiescent current. this industry leading low current solution can be further reduced when needed using the optional power shutdown to <0.4ma supply current. external feedback and gain setting resistors give maximum flexibility and accuracy. a companion device, the isl55211, includes on-chip feedback and 3 possible gain setting connections where an inte rnally fixed gain solution is preferred. the ISL55210 is available in a leadless, 16 ld tqfn package and is specified for operation over the -40oc to +85oc ambient temperature range. features ? gain bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . 4.0ghz ? input voltage noise . . . . . . . . . . . . . . . . . . . . . . . 0.85nv/ (hz) ? differential slew rate . . . . . . . . . . . . . . . . . . . . . . . 5,600v/s ?2v p-p , 2-tone im3 (200 ? ) 100mhz . . . . . . . . . . . . . . -109dbc ? supply voltage range . . . . . . . . . . . . . . . . . . . . . . 3.0v to 4.2v ? quiescent power (3.3v supply) . . . . . . . . . . . . . . . . . .115mw applications ? low power, high dynamic range adc interface ? differential mixer output amplifier ? saw filter pre/post driver ? differential comms-dac output driver related products ? coming soon : isl55211 - fixed gain version of the ISL55210 ? isla112p50 - 12-bit, 500msps adc (<500mw) ? coming soon : isla214p50 - 14-bit, 500msps adc (<850mw) snrfs = 64. 9dbfs hd2 = -83dbc hd3 = -84dbc enobfs = 10.5 bits figure 1. typical application circuit 0.1f 1:2 ISL55210 +3.3v + - vcm 20pf 20pf 33nh 33nh v+ v- isla112p50 adt4-1wt 0.1f 0.1f v b clk 500msps 105mhz single tone 180mv pp for -1dbfs 35ma (115mw) v i 12 bit <500mw 500khz v diff v i v diff = 17.3db gain 180mhz span 20log ( ) pd 100 50 100 495 495 210 210 40.2 10k 40.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. march 2, 2011 fn7811.0
ISL55210 2 fn7811.0 march 2, 2011 pin configuration ISL55210 (3x3 16 ld tqfn) top view gnd nc nc gnd gnd v cm fb+ v s+ 1 2 3 4 56 78 9 10 11 12 13 14 15 16 + - v cm v i - gnd gnd v i + fb- v o+ v o- v s+ pd pin descriptions pin number symbol description 1 fb+ positive output feedback resistor connection 2v i- inverting amplifier input 3v i+ noninverting amplifier input 4 fb- negative output feedback resistor connection 5, 8, 13, 16 gnd supply ground (thermal pad electrically connected) 6, 15 v s+ positive power supply (3.0v~4.5v) 7pd power-down: pd = logic low puts part into low power mode, pd = logic high or 1k ? to v s+ for normal operation 9v o- inverting amplifier output 10, 11 nc no internal connection 12 v o+ noninverting amplifier output 14 v cm common-mode voltage input ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) transport media, quantity pkg. dwg. # ISL55210irtz 5210 -40 to +85 16 ld 3x3 tqfn l16.3x3d ISL55210irtz-t7 5210 -40 to +85 16 ld 3x3 tqfn tape and reel, 1000 l16.3x3d ISL55210irtz-t7a 5210 -40 to +85 16 ld 3x3 tqfn tape and reel, 250 l16.3x3d ISL55210irtz-evalz evaluation board (contact local sales) notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs comp liant and compatible with both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL55210 . for more information on msl please see techbrief tb363 .
ISL55210 3 fn7811.0 march 2, 2011 absolute maximum ratings (t a = +25c) thermal information supply voltage from v s+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v s+ +0.3v to gnd-0.3v power dissipation (see ?power supply, shutdown, and thermal considerations? on page 13) esd rating human body model (per mil-std-883 method 3015.7) . . . . . . . . 3500v machine model (per eiaj ed-4701 method c-111) . . . . . . . . . . . . . 250v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500v latch up (per jesd-78; class ii; level a) . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 16 ld tqfn package (notes 4, 5) . . . . . . . 63 16.5 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +125c maximum continuous operating junction temperature. . . . . . . . . . .+135c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient operating temperature . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v s+ = +3.3v test conditions: g = 12db, v cm = open, v o = 2v p-p , r f = 200 ? , r l = 200 ? differential, t a = +25c, differential input, differential output, input and output referenced to internal default v cm (1.2v nominal) unless otherwise specified. parameter conditions min (note 6) typ max (note 6) unit tested (note 7) ac performance small-signal bandwidth (4-port s parameter, test circuit #2) g = 12db, v o = 100mv p-p 2,200 mhz g = 18db, v o = 100mv p-p 700 mhz g = 24db, v o = 100mv p-p 300 mhz gain-bandwidth product g = 18db 4.0 ghz bandwidth for 0.1-db flatness g = 12db, v o = 100mv p-p 200 mhz large-signal bandwidth g = 12db, v o = 2v p-p 1.2 ghz slew rate (differential) 5,600 v/s differential rise/fall time 2-v step 0.17 ns 2nd-order harmonic distortion f = 20mhz, v o = 2v p-p -105 dbc f = 50mhz, v o = 2v p-p -88 dbc f = 100mhz, v o = 2v p-p -72 dbc 3rd-order harmonic distortion f = 20mhz, v o = 2v p-p -120 dbc f = 50mhz, v o = 2v p-p -107 dbc f = 100mhz, v o = 2v p-p -95 dbc 2nd-order intermodulation distortion f c = 70mhz, 200khz spacing (2v p-p envelope) -80 dbc f c = 140mhz, 200khz spacing (2v p-p envelope) -68 dbc 3rd-order intermodulation distortion f c = 70mhz, 200khz spacing (2v p-p envelope) -102 dbc f c = 140mhz, 200khz spacing (2v p-p envelope) -94 dbc input voltage noise f > 1mhz, differential 0.85 nv/ hz input current noise f > 1mhz, each input 5.0 pa/ hz
ISL55210 4 fn7811.0 march 2, 2011 dc performance open-loop voltage gain (a ol )differential 86100 db* input offset voltage t a = +25c -1.4 0.1 +1.4 mv * t a = -40c to +85c -1.6 0.1 +1.6 mv average offset voltage drift t a = -40c to +85c 3 v/ c input bias current t a = +25c, positive current into the pin +50 +120 a * t a = -40c to +85c +50 +140 a average bias current drift t a = -40c to +85c +200 na/ c input offset current t a = +25c -5 1 +5 a * t a = -40c to +85c -6 1 +6 a average offset current drift t a = -40c to +85c 8 na/ c input common-mode input range high 1.7 v * common-mode input range low 1.1 v * common-mode rejection ratio f < 10mh z, common mode to differential output 56 75 db * differential input impedance 1 || 2k ? || pf output maximum output voltage each output (with 200 ? differential load) linear operation 2.15 2.35 v * minimum output voltage 0.45 0.63 v * differential output voltage swing t a = +25c 3.04 3.8 v p-p * t a = -40c to +85c 2.95 v differential output current drive r l = 10 ? [sourcing or sinking] 40 45 ma * closed-loop output impedance f < 10mhz, differential 0.6 ? output common-mode voltage control small-signal bandwidth from v cm pin to output v cm 30 mhz slew rate rising/falling 150 v/s gain v cm input pin 1.0v to 1.4v 0.995 0.999 v/v * output common-mode offset from cm input -8 1 +8 mv * cm default voltage output v cm with v cm pin floating 1.18 1.2 1.22 v * cm input bias current at control pin 2 a cm input voltage range at control pin 0.9 1.9 v * cm input impedance at control pin 15 || 50 k ? || pf power supply specified operation voltage 3 3.3 4.2 v quiescent current t a = +25, v s+ = 3.3v, v s- = 0v 33 35 37 ma * t a = -40c to +85c 30.5 36 39.5 ma power-supply rejection (psrr) v s+ 3.0v - 4.5v range 56 90 db * electrical specifications v s+ = +3.3v test conditions: g = 12db, v cm = open, v o = 2v p-p , r f = 200 ? , r l = 200 ? differential, t a = +25c, differential input, differential output, input and output referenced to internal default v cm (1.2v nominal) unless otherwise specified. (continued) parameter conditions min (note 6) typ max (note 6) unit tested (note 7)
ISL55210 5 fn7811.0 march 2, 2011 power-down referenced to gnd enable voltage threshold assured on above 1.55v 1.3 1.55 v * disable voltage threshold assured off below 0.54v 0.54 0.7 v * power-down quiescent current t a = +25c 0.2 0.3 0.4 ma * t a = -40c to +85c 0.15 0.3 0.45 ma input bias current pd = 0v, current positive into pin -2 a input impedance 2 || 5m ? || pf turn-on time delay measured to output on 200 ns turn-off time delay measured to output off 400 ns notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization, and/or design. 7. parameters denoted by an ?*? are ate tested. electrical specifications v s+ = +3.3v test conditions: g = 12db, v cm = open, v o = 2v p-p , r f = 200 ? , r l = 200 ? differential, t a = +25c, differential input, differential output, input and output referenced to internal default v cm (1.2v nominal) unless otherwise specified. (continued) parameter conditions min (note 6) typ max (note 6) unit tested (note 7)
ISL55210 6 fn7811.0 march 2, 2011 typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. figure 2. frequency resp onse vs gain setting figure 3. frequency response vs output swing figure 4. im2 and im3 vs gain figure 5. output v p-p for -1db gain compression figure 6. noise figure figure 7. noise figure at higher gains -24 -21 -18 -15 -12 -9 -6 -3 0 3 6 10 7 10 8 10 9 frequency (hz) 27db normalized gain (db) 15db 21db 33db test circuit #1, r l = 200 ? , v o = 500mv p-p differential 9 12 15 18 3 6 10 6 10 7 10 8 10 9 frequency (hz) gain (db) test circuit #1 input transformer v o = 3v p-p slew limiting v o = 1v p-p +2v p-p -125 -115 -105 -95 -85 -75 -65 50 100 150 200 250 test frequencies center (mhz) 2-tone im spurious (dbc) test circuit #1, r l = 200 ? , vo p-p = 1v p-p each tone im2 21db gain im3 15db gain im2 15db gain im3 21db gain 3.0 3.5 4.0 4.5 5.0 5.5 6.0 50 100 150 200 250 frequency (mhz) output compression point r l = 200 ? r l = 100 ? r l = 50 ? test circuit #1 (v p-p , differential) 6 7 8 9 10 11 12 50 200 350 500 frequency (mhz) noise figure (db) gain = 15db gain = 21db test circuit #1 6 7 8 9 10 11 12 50 200 350 500 frequency (mhz) noise figure (db) gain = 18db gain = 24db test circuit #1 with adt4-1t input and r g = 100 ? , r f = 400 ?
ISL55210 7 fn7811.0 march 2, 2011 figure 8. hd2/hd3 vs v opp figure 9. im2 and im3 vs output swing figure 10. hd2 and hd3 vs gain figure 11. im2 and im3 vs gain figure 12. hd2 and hd3 vs r load figure 13. im2 and im3 vs r load typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) -120 -110 -100 -90 -80 -70 -60 20 100 frequency (mhz) hd2/hd3 spurious (dbc) hd2 3v p-p hd2 2v p-p hd2 1v p-p hd3 3v p-p hd3 1v p-p hd3 2v p-p 200 test circuit #1, r l = 200 ? -120 -110 -100 -90 -80 -70 -60 20 100 200 test frequencies center (mhz) test circuit #1, r l = 200 ? im3 1v p-p im3 2v p-p im3 3v p-p im2 1v p-p im2 2v p-p im2 3v p-p im2 and im3 spurious (dbc) -120 -110 -100 -90 -80 -70 20 100 200 frequency (mhz) hd2, gain = 21db hd3, hd3, hd2 and hd3 distortion (dbc) -60 gain = 15db test circuit #1 gain = 21db hd2, gain = 15db hd2, hd3, gain = 27db gain = 27db hd2, gain = 21db -125 -115 -105 -95 -85 -75 -65 20 100 200 test frequencies center (mhz) test circuit #1 im3 gain = 15db im3 im3 gain = 27db im2 gain = 15db im3 gain = 21db im3 gain = 27db gain = 21db im2 and im3 spurious (dbc) -120 -110 -100 -90 -80 -70 -60 -50 20 100 200 frequency (mhz) hd3, 500 ? hd3, 200 ? hd3, 100 ? hd2, 50 ? distortion (dbc) hd3, 50 ? hd2, 500 ? hd2, 200 ? hd2, 100 ? -120 -110 -100 -90 -80 -70 -60 -50 20 100 200 center frequency (mhz) im3, 500 ? im3, 200 ? im3, 100 ? im spurious (dbc) im2, 500 ? im2, 200 ? im2, 100 ? im2, 50 ?
ISL55210 8 fn7811.0 march 2, 2011 figure 14. phase and group delay vs gain figure 15. input voltage and current spot noise figure 16. small signal response vs gain figure 17. differential output impedance figure 18. v cm pin input frequency response to output common mode figure 19. output balance error typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 45 60 75 90 105 120 135 150 165 180 10 40 70 100 130 160 190 frequency (mhz) group delay (ns) phase () group delay group delay, g = 27db phase, g = 15db phase g = 21db group delay g = 15db g = 21db phase g = 27db test circuit #2 0.1 1.0 10.0 10 5 10 6 10 7 10 8 frequency (hz) e n (differential) i n (each input) voltage noise (nv/ hz) and current noise (pa/ hz) -21 -18 -15 -12 -9 -6 -3 0 3 frequency (hz) normalized differential gain (db) r f = 1.6k ? r f = 402 ? r f = 200 ? r f = 806 ? 10 9 10 7 10 8 4-port s21 test, test circuit #2 0 1 2 3 4 5 6 7 8 9 10 1 10 100 1000 closed loop output impedance ( ? ) frequency (mhz) simulated test, test circuit #2 gains 12db to 30db -21 -18 -15 -12 -9 -6 -3 0 3 110 frequency (mhz) 200mv p-p 10mv p-p gain (db) 100 200 test circuit #3 common mode ac output -75 -70 -65 -60 -55 -50 -45 2 10 100 200 test frequency (mhz) output v cm vs v diff (db) test circuit #3 common mode ac output measurements
ISL55210 9 fn7811.0 march 2, 2011 figure 20. small signal step response figure 21. large signal step response figure 22. enable/disable times figure 23. disabled feedthrough figure 24. overdrive recovery figure 25. psrr/cmrr to differential v o typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 1020304050 timebase (ns) input output amplitude (v) test circuit #1, 50mhz square wave input -1.5 -1.0 -0.5 0 0.5 1.0 1.5 0 5 10 15 20 25 30 35 40 45 50 time (ns) amplitude (v) input output test circuit #1, 50mhz square wave input pd 100mhz output disabled enabled 2s/div test circuit #1 -16 -14 -12 -10 -8 -6 -4 -2 0 110100 frequency (mhz) 100mv p-p input 2v p-p input feedthrough (db) test circuit #1 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 180 200 time (ns) input and output wafeforms (v) output input test circuit #1 1 10 100 1000 frequency (mhz) psrr/cmrr (db) 35 45 55 65 75 85 95 test circuit #1 simulated, exact external r?s psrr to v o (differential) cmrr to v o (differential)
ISL55210 10 fn7811.0 march 2, 2011 applications basic operation the ISL55210 is a very wideband, voltage feedback based, differential amplifier including an output common mode control loop and optional power shutdown feature. intended for very low distortion differential signal driving, this non-unity gain stable device also delivers extremely low input noise terms of 0.85nv/ hz and 5pa/ hz . most applications are intended for ac coupled i/o using a single 3.3v supply. it will operate over a single supply range of 3.0v to 4.2v. where dc coupled operation is desired, using split power supplies will allow the ISL55210 i/o common mode range limits to be observed while giving either a differential i/o or single to differential configuration. most applications behave as a diff erential inverting op amp design. there is, therefore, an input gain resistor on each side of the inputs that must be driven. to retain overall low output noise, these resistors are normally of low value. the device can be powered down to <400a supply current using the optional disable pin. to operate normally, this pin should be asserted high using a simple logic gate to +v s or tied high through a 10k ? resistor to +v s . when disabled, the power dissipation drops to <1mw but, due to the inverting op amp type architecture, the input sign al will feed forward through the external resistors giving limited isolation. application and charac terization circuits the circuit of figure 28 forms a starting point for many of the characterization curves for the ISL55210. since most lab sources and measurement devices are single -ended, this circuit converts to differential at the input th rough a wideband transformer and would also be a typical applicatio n circuit coming from a single ended source. assuming the source is a 50 ? impedance, the r g resistors are set to provide both the input termination and the gain. since the inverting summing nodes act as virtual ground points for ac signal analysis, the total termination impedance across the input transformer secondary will be 2 * r g . setting this equal to n 2 *r s will give a matched input impedance inside the bandwidth of the transformer (where "n" is the turns ratio). the amplifier gain is then set by adjusting the feedback resistors values. since the ISL55210 is a vfa design, increasing the feedback resistor to get higher ga in does not directly reduce the bandwidth as it would with a cfa based design. this gives increased flexibility in the input turns ratio and overall gain setting (while holding a matched input impedance) over alternate solutions. working with a transformer coupled input as shown in figure 28, or with two dc blocking caps fr om a differential source, means the output common mode voltage set by either the default internal v cm setting, or a voltage applied to the v cm control pin, will also appear as the inpu t common mode voltage. this provides a very easy way to control the ISL55210 i/o common mode operating voltag es for an ac coupled signal path. the internal common mode loop holds the output pins to v cm and, since there is no dc path for an i cm current back towards the input in figure 28, that v cm setting will also appear as the input common mode voltage. it is usef ul, for this reason, to leave any input transformer secondary centertap unconnected. the internally set v cm voltage is referenced from the negative supply pin. with a single 3.3v supply, it is very close to 1.2v but will change with total supply voltag e across the device as shown in figure 26. figure 26. default v cm and max v opp vs supply voltage figure 27. supply current vs supply voltage typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) 1 2 3 4 5 6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 supply voltage (v) test circuit #1 internally set v cm maximum differential v p-p output using default v cm output default v cm and max differential v opp (v) 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 single supply voltage (v) test circuit #1 t a = +25c t a = -40c t a = +85c supply current (ma) 50 1:1.4 1f 1f 85 ISL55210 +3.3v + - v i 50 50 35 35 adt2-1t 0.1uf 200 v cm 200 200 33ma 110mw 1:1 adt1-1wt 50 1f v m v o r g r g r f r f 10k pd 200 load 85 1f figure 28. test circuit #1
ISL55210 11 fn7811.0 march 2, 2011 most of the characterization curves start with figure 28 then get different gains by changing the feedback resistor, r f , use different input transformers where then the r g is also adjusted to hold an input match, or vary the loading. for load tests below the 200 ? shown in figure 28, a simple added shunt resistor is placed across the output pins. for loads >200 ? , the series and shunt load r's are adjusted to show that total load (including the 50 ? measurement load reflected through the 1:1 output measurement port transformer) and provide an apparent 50 ? differential source to that tr ansformer. this output side transformer is for measurement purposes only and is not necessary for final applications circuits. there are output interface designs that do benefit from a transformer as part of the signal path, but the one shown at the right of figure 28 is used only for characterization to get a doubly terminated 50 ? measurement path going differential to single ended. where just the amplifier is tested, a 4 port network analyzer is used and the very simple te st circuit of figure 29 is implemented. this is used to extract the differential s21 curves and differential output impedance vs gain. changing the gain is a simple matter of adjusting the two r f resistors of figure 29. this circuit depends on the two ac coupled source 50 ? of the 4 port network analyzer and presents an ac coupled differential 100 ? load to the amplifier as the input impedance of the remaining two ports of the network analyzer. using this measurement allows th e full small single bandwidth of the ISL55210 to be exposed. many of the other measurements are using i/o transformers that are lim iting the apparent bandwidth to reduced level. figure 16 shows a series of normalized differential s21 curves for gains of 12db to 30db in 6db steps. these are simply stepping two feedback resistor values (r f ) up from 200 ? to 1600 ? in 2x steps. the lowest gain of 12db (4v/v) is showing a 2.2ghz small signal bandwidth. this response gets some bandwidth extension due to phase margin <60degree effects, but by the gain of 24db (16v/v), th e bandwidth is following a gain bandwidth type characteristic showing 300mhz bandwidth or >4ghz gain bandwidth product (gbp). the closed loop differential output impedance of figure 17 is simulated using figure 29 in ads. this shows a relatively low output impedance (<1 ? through 100mhz) constant with signal gain setting. typical fda outputs show a closed loop output impedance that increases with si gnal gain setting. the ISL55210 holds a more constant response vs gain due to internal design elements unique to this device. common mode output measurements are made using the circuit figure 30. here, the outputs are summed together through two 100 ? resistors (still a 200 ? differential load) to a center point where the average, or common mode, output voltage may be sensed. this is coupled through a 1f dc blocking capacitor and measured using 50 ? test equipment. the common mode source impedance for this circuit is the parallel combination of the 2 ? -100 ? elements, or 50 ? . figure 18 uses this circuit to measure the small and large si gnal response from the v cm control pin to the output common mode. this pin includes an internal 50pf capacitor on the default bias network (to filter supply noise when there is no connection to this pin) which bandlimits the response to approximately 30mhz. this is far lower than the actual bandwidth of the common mode loop. figure 19 uses this output cm measurement circuit with a large signal (2v p-p ) differential output volt age (generated through the v i path of figure 30) to measure the differential to common mode conversion. single supply, input transformer coupled, design considerations the characterization circuit of figure 28 shows one possible input stage interface that offers several advantages. the ISL55210 can also support a dc coupled differential to differential or single ended input to differential requirement if needed. where ac coupling is adequate, the circuit of figure 28 simplifies the input common mode voltage control. if the source coming into this stage is single ended, the input transformer provides a zero power conversion to differential. the two gain resistors (r g in figure 28) provide both the input termination impedance and the gain element for the amplifier. for minimum noise, only r g should be used and set to achieve the desired input impedance. since the ISL55210 is a vfa device, these resistor values can be scaled up and down a bit more freely than a current feedback based fda. figure 29. test circuit #2 4-port s-parameter measurements ISL55210 +3.3v + - v cm r f r f 1/2 of a 4-port s-parameter pd 50 10k 50 50 50 1/2 of a 4-port s-parameter figure 30. test circuit #3 common mode ac output measurements 1f 1:1.4 ISL55210 +3.3v + - v cm adt2-1t 1f v i pd output v cm v cm input 100 100 10k 50 50 50 50 50 50 200 200
ISL55210 12 fn7811.0 march 2, 2011 for instance, if a minimum noise configuration is not required, but it is desirable to increase the feedback resistors to reduce the added loading they present to the output stage, the r g and r f resistors can be scaled up to achieve the same gain with an additional termination resist ance added across the input transformer to adjust the termination impedance. figure 31 shows an example using a 1:2 input turns ratio where the r g and r f elements have been scaled up and a shunt termination resistance added. this example provides a single to differential signal gain of 20db and input impedance of 50 ? to the source. the 1:2 turn ratio transformer needs a 200 ? differential secondary impedance to provide an input side 50 ? match. this is provided here by the parallel combination of the 2 ? -200 ? r g resistors and the 400 ? parallel impedance at the transformer secondary. this circuit has scaled the feedback resistor up to 1k ? to still achieve the amplifier gain of 5v/v which gives the overall gain of 10v/v (20db) when the 1:2 step up at the input is considered. the particular transformer shown is typical of 1:2 turns ratio broadband transformers, but ther e a many alternates with the similar or improved characteristics. this input interface also simplifies the input common mode control. the v cm pin controls the output common mode voltage. in most dc coupled fda applications, the input common mode voltage is determined by both this output common mode and the source signal. in a configuration like figure 31, there is no path for a common mode current to flow from output to input, so the input common mode voltage equals the output. a similar effect could be achieved with just two blocking caps on the two r g resistors. a dc coupled, single to differential, configuration will also have a common mode input that is moving with the input signal. converting to just a differen tial signal at th e amplifier, as in figure 31, removes any input signal related artifacts from the input common mode making the ISL55210 behave as a differential only vfa amplifier. there is only a very small differential error signal at the inpu ts set by the loop gain, as in a normal single ended vfa applic ation, but no common mode signal related terms. the examples shown are using the transformer to convert from single to differential. howeve r, if the source is already differential, these same transformer input circuits can drive the transformer differentially still providing impedance scaling if needed and common mode rejection for both dc and ac common mode issues. a good example would be differential mixer outputs or saw filter outp uts. those differential sources could also be connected into the ISL55210 r g resistors through blocking caps as well eliminating the input transformer. the ac termination impedance for the differential source will then be the sum of the two r g resistors when simple blocking caps are used. amplifier i/o range limits the ISL55210 is intended principally to give the lowest im3 performance on the lowest power for a differential i/o application. the amplifier will work dc coupled and over a relatively wide supply range of 3.0v to 4.2v supplies. the outputs have both a differential and common mode operating range while the input pins have a common operating range. for single supply operation, the ground pins are at ground as is the exposed metal pad on the underside of the package. the ISL55210 can operate split supply where then the ground pins will be a negative supply voltage and the exposed metal pad is either connected to this negative supply or left unconnected on an insulating board layer. briefly, the i/o and v cm limits are: 1. maximum v cm setting = -v s + 2v 2. input common mode operating range of -v s + 1.1v or the output v cm + 0.5v 3. output v o minimum (on each side) is either -v s + 0.3v or output v cm - 0.9v 4. output v o maximum (on each side) is +v s - 1.5v the output swing limits are often asymmetrical around the v cm voltage. the maximum single ended swings are set by these two limits: v omin is either -v s + 0.3v or v cm - 0.9v whichever is less. so for instance on a single 3.3v supply with the default v cm voltage of 1.2v, these two limits give the same result and the output pins can swing down to 0.3v above -v s = 0v. if, however, the v cm pin is raised to 1.5v, then the minimum output voltage will become 1.5v - 0.9v = 0.6v. v omax is set by a headroom limit to the positive supply to be: v omax = +v s - 1.5v. again, on a 3.3v single supply and the default 1.2v v cm setting, this mean the maximum referenced to ground output pin voltages can be 3.3v - 1.5v = +1.8v or 0.6v above the default v cm voltage. using these default conditions, and the maximum positive excursion of 0.6v above the 1.2v output v cm setting, the maximum differential v p-p swing will be 4x this 0.6v single ended limit or 2.4v p-p . where +v s is increased the limit then becomes the 0.9v below v cm , but then the absolute maximum differential v p-p is then 4x 0.9v to 3.6v p-p . so, for instance, to get this maximum output swing, in crease the supply voltage until +v s - 1.5v > v cm + 0.9v. if we assume a v cm voltage of 1.3v for instance, then 1.3v + 0.9v + 1.5v = 3.7v will give an unclipped figure 31. single to differential with reduced feedback loading 1f 1:2 ISL55210 +3.3v + - v i adt4- 1wt v cm v o r f r f r g r g 50 1k 1k 200 200 400
ISL55210 13 fn7811.0 march 2, 2011 3.6v p-p output capability. the v p-p reported in figure 26 is an asymmetrically clipped maximum swing. going 10% above this 3.7v target to 4.1v will be within the recommended operating range and give some tolerancin g headroom that would also suggest the v cm voltage be moved up to approximately 1.5v. this coincides with the default output v cm from figure 26. operating at +4.1v single supply in a figure 28 type configuration will give the maximum linear available output swing of 3.6v p-p . the differential inputs of the ISL55210 also have operating range limits relative to the supply voltages. operating in an ac coupled circuit like figure 28 will produce an input common mode voltage equal to the output s. the inputs can operate with full linearity with this v cm voltage down to 1.1v above the gnd connection (or -v s supply). on the default 1.2v output v cm on +3.3v supplies this gives a 100mv guardband on the input v cm voltages. overriding the default v cm by applying a control voltage to the v cm pin should be done with care in going towards the negative supply due to this limit. on the + side, the maximum v cm above the -v s supply is 2v so there is more room to move the output v cm up than down from the default value. when operated as a dc coupled si ngle to differential amplifier, the input common mode voltage w ill move with the input signal and will be different than the output common mode voltage when the external resistors are set for gain. when the input common mode can be different than the output, the additional constraint that must be observed is that the input common mode voltage cannot be > output v cm +0.5v. this would only occur if the single source was coming fr om a higher voltage than the output v cm setting. power supply, shutdown, and thermal considerations the ISL55210 is intended for single supply operation from 3.0v to 4.2v with an absolute maximum setting of 4.5v. the 3.3v supply current is trimmed to be nominally 35ma at +25c ambient. figure 27 shows the supply current for nominal +25c and -40c to +85c operation over the specified maximum supply range. the input stage is biased from an internal voltage referenced from the negative su pply giving the exceptional 90db low frequency psrr shown in figure 25. since the input stage bias is from a re-regulated internal supply, a simple approach to single +5v operation can be supported as shown in figure 32. here, a simple ir drop from the +5v supply will bring the operating supply voltage for the ISL55210 into its allowed range. figure 32 show s example calculations for the voltage range at the ISL55210 +v s pin assuming a 5% tolerance on the +5v supply and a 35ma to 55ma range on the total supply current. considerin g the 34ma to 44ma quiescent current range from figure 27 ov er the -40c to +85c ambient, and the 3.4v to 4.4v supply voltage range assumed here, this is designing for a 1ma to 11ma aver age load current which should be adequate for most intended application loads. good supply decoupling at the device pins is required for this simple solution to still provide exceptional sfdr performance. the ISL55210 includes a power shutdown feature that can be used to reduce system power dissipation when signal path operation is not required. this pin (pd ) is referenced to the ground pins and must be asserted low to activate the shutdown feature. when not used, a 10k ? external resistor to +v s should be used to assert a high level at this pin. digital control on this pin can be either an open collector output (using that 10k ? pullup) or a cmos logic li ne running off the same +v s as the amplifier. for split supply operation, the pd pins must be pulled to below -v s + 0.54v to disable. since the ISL55210 operates as a differential inverting op amp, there is only modest signal pa th isolation when disabled as shown in figure 23. for small input signals, figure 23 shows about 5db to 6db isolation while for large signals, back to back protection diodes across the inputs compress the signal to show actually an improved isolation. this is intended to protect any subsequent devices from large input signals during shutdown. those diodes limit the maximum overdrive voltage across the input to approximately 0.5v in each polarity. the r g resistors of test circuit #1 limit the current into those diodes under this condition. the supply current in shutdown does not reduce to zero as internal circuitry is still active to hold the output common mode voltage at the v cm control input voltage even during shutdown (or the default value). this is intended to hold the ISL55210 output near the desired common mode output level during shutdown. this improves turn on characteristic and keeps the output voltages in a safe range for downstream circuitry. the very low internal power dissipation of the ISL55210, along with the excellent thermal conduc tivity of the qfn package when the exposed metal pad is tied to a conductive plate, reduces the t j rise above ambient to very mo dest levels. assuming a nominal 115mw dissipation and using th e +63c/w measured thermal impedance from junction to ambient, gives a rise of only 0.12 * 63 = +7.6c. operation at elevated ambient temperatures is easily supported given this very low internal rise to junction. figure 32. operating from a single +5v supply c in 1:n ISL55210 +5v 5% + - v i v cm v o r f r f r g r g pd r o r o 35 55ma 3.4 4.4v 10nf 2.2f + 10k 24.3
ISL55210 14 fn7811.0 march 2, 2011 the maximum internal junction temperatures would occur at maximum supply voltage, +85c maximum ambient operating, and where the qfn exposed pad is not tied to a conductive layer. where the qfn must be mounted with an insulating layer to the exposed metal plate, such as in a split supply application, device measurements show an increased thermal impedance junction to ambient of +120c/w. using this, and a maximum quiescent internal power on 4.5v absolute maximum, which shows 45ma for +85c maximum operating ambient from figure 27, we get 4.5v * 45ma * +120c/w = +24c rise above +85c or approximately +10 9c operating t j maximum - still well below the specified absolute maximum operating junction temperature of +135c. noise analysis the decompensated voltage feedback design of the ISL55210 provides very low input voltage and current noise. while a detailed noise model using arbitrary external resistors can be made, most applications will have a balanced feedback network with the two r f (feedback) resistors equal and the two r g (gain) resistors equal. figure 33 shows the test circuit used to measure the output noise with the noise terms detailed. the aim here was to measure the output noise with two different resistor settings to extract out a model for the input referred en and in terms for just the amplifier itself. with equal feedback and gain resistors, the total output noise expression becomes very simple. this is: the ng term in equation 1 is the noise gain = 1 + r f /r g . the last term in equation 1 captures both the r f and r g resistor noise terms. if we assume a 50 ? source in test circuit #1, the total r g resistor value will be 100 ? as that 50 ? will come through the transformer to look like a 50 ? source on each side. this gives a lower noise gain (3v/v) than signal gain (4v/v) for just the amplifier. the total gain in test circuit #1 is still approximately 1.4 * 4 = 5.6v/v including the transformer step up. putting in ng = 3, r f = 200 ? , r g = 100 ? with the ISL55210 noise terms of en = 0.85nv/ hz and in = 5pa/ hz into equation 1 (4kt = 1.6e - 20j) gives a total output differential noise voltage = 5.26nv/ hz. input referring this to the input side of the transformer of test circuit #1 give s an input referred spot noise of only 0.88nv/ hz. this extremely low input referred noise is a combination of low amplifier nois e terms and the effect of the input transformer configuration. driving cap and filter loads most applications will drive a resistive or filter load. the ISL55210 is robust to direct capacitive load on the outputs up to approximately 10pf. for frequency re sponse flatness, it is best to avoid any output pin capacitance as much as possible - as that capacitance increases, the high frequency portion of the ISL55210 (>1ghz) response will start to show considerable peaking. no oscillations were observed up through 10pf load on each output. for ac coupled applications, an output network that is a small series resistor (10 ? to 50 ? ) into a blocking cap is preferred. this series resistor will isolate para sitic capacitance to ground from the internally closed loop outp ut stage of the amplifier and de-queue the self resonance of the blocking capacitors. once the output stage sees this resistive element first, the remaining part of the filter design can be done without fear of amplifier instability. driving adcs many of the intended applications for the ISL55210 are as a low power, very high dynamic range, last stage interface to high performance adcs. the lowest power adcs, such as the isla112p50 shown on the front page, include an innovative "femto-charge" internal architec ture that eliminates op amps from the adc design and only passe s signal charge from stage to stage. this greatly reduces the required quiescent power for these adcs but then that signal ch arge has to be provided by the external circuit at the two input pi ns. this appears on an adc like the isla112p50 as a clock rate dependent common mode input current that must be supplied by the interface circuit. at 500mhz, this dc current is 1.3ma on each input for the isla112p50 . most interfaces will also include an interstage noise power bandlimiting filter between the am plifier and the adc. this filter needs to be designed considering the loading of the amplifier, any v cm level shifting that needs to take place, the filter shape, and this i cm issue into the adc input pins. here are 4 example topologies suitable for different situations. 1. ac coupled, broadband rlc interstage filter design. this approach lets the amplifier op erate at its desired output common mode, then provides the adc common mode voltage and current through a bias path as part of the filter design?s last stage r values. the v b is set to include the ir loss from that voltage to the adc inputs due to the i cm current. this circuit is the one shown on the front page where we get a usable frequency range from about 500khz to 150mhz. figure 33. noise model and test circuit 1f ISL55210 + - e o r f r f r g r g 1f * i n * * 4ktr g 4ktr g * i n * 4ktr f 4ktr f * * e n 1f 1:1 adt1-1wt 50 25 25 (eq. 1) e 0 e n ng ? () 2 2 + i n r f () 2 24ktr f ng () + =
ISL55210 15 fn7811.0 march 2, 2011 2. ac coupled, higher frequency range interstage filter design. this design replaces the r t resistors in figure 34 with large valued inductors and implements the filter just using shunt resistors at the end of the rlc filter (here, that is just the adc internal differential rin). in this case, the adc v cm can be tied to the centerpoint of the bias pa th inductors (very much like a bias-t) to provide the common mode voltage and current to the adc inputs. these bias inductors do limit the low frequency end of the operation where, with 1h values, operation from 10mhz to 200mhz is supported using the approach of figure 35. 3. ac coupled with output side tr ansformer. this design includes an output side transformer, very similar to adc characterization circuits. this ap proach allows a slightly lower amplifier output swing (if n > 1 is used) and very easy 2nd order low pass responses to be im plemented. it also provides the i cm and v cm bias to the adc th rough the transformer centertap. this approach would be attractive for higher adc input swing targets and more aggressive noise power bandwidth control needs. 4. dc coupled with adc v cm and i cm provided from the amplifier. here, dc to very high frequency interstage low pass filters can be provided. again, the r s element must be low to reduce the ir drop from the v cm of the converter, which now shows up on the output of the ISL55210, to the adc input pins. in this case, split supplie s are required to satisfy the amplifier output and input common mode range limits discussed earlier. figure 34. ac coupled, broadband rlc interstage filter design figure 35. ac coupled, higher frequency rlc filter design figure 36. ac coupled with output side transformer figure 37. dc coupled with a common v cm voltage from the adc ISL55210 v cm1 r s r s r f r f +3.3v 1.2v c b c b r t r t icm icm c t c t r in c in adc s r t r > v cm2 = 0.535 or 1v l s l s v b 2 cm v t r cm i b v = ? in+ in- r t r s > v b i cm r t ? v cm2 = ls lp >> ISL55210 v cm1 r s r s r f r f +3.3v 1.2v c b c b r t i cm i cm c t c t r in c in adc in+ in- v cm2 = 0.535 or 1v l s l s l p l p 2i cm 30 rt ISL55210 v cm1 r s r s r f r f +3.3v 1.2v c b c b r t r t i cm i cm c t c t r in c in adc v cm2 = 0.535 or 1v in+ in- 1:n 30 rs ISL55210 r s r s r f r f +3.0v r t icm icm c t c t r in c in adc v cm = 0.535v or 1v l s l s in+ in- v cm -1.1v
ISL55210 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7811.0 march 2, 2011 for additional products, see www.intersil.com/product_tree layout considerations the ISL55210 pinout is organized to isolate signal i/o along one axis of the package with ground, power and control pins on the other axis. ground and power should be planes coming into the upper and lower sides of the pack age (see the pin configuration on page 2). the signal i/o should be laid out as tight as possible with parasitic c to the ground and/or power planes reduced as much as possible by opening up those planes under the i/o elements. the ground pins and package backside metal contact should be connected into a good ground plane. the power supply should have both a large value electrolytic cap to ground, then a high frequency ferrite beads, then 0.01f smd ceramic caps at the supply pins. some improvement in hd2 performance may be experienced by placing and x2y cap between the two v s+ pins and ground underneath the package on the board back side. this is 4 terminal device that is included in the evm board layout. evm board (rev. c) test circuit #1 (figure 28) is implemented on an evaluation module board available from intersil. this board includes a number of optional features that are not populated as the board is delivered. the full evm board circuit is shown in figure 38 where unloaded (optional) elements are shown in green. the nominal supply voltage for the board and device is a single 3.3v supply. from this, the ISL55210, isl55211 generates an internal common mode voltage of approximately 1.2v. that voltage can be overridden by populating the two resistors and potentiometer shown as r19 to r21 above. the primary test purpose for this board is to implement different interstage differential passive filters intended for the adc interface along with the adc input impedances. the board is delivered with only the output r's loaded to give a 200 ? differential load. this is done using the two 85 ? resistors as r9 and r10, then the 4 zero ohm elem ents (r10, r12, r24, and r25) and finally the two shunt elements r13 and r14 set to 35.5 ? . including the 50 ? measurement load on the output side of the 1:1 transformer reflecting in parallel with the two 35 ? resistors takes the nominal ac shunt impedance to 71 ? ||50 ? = 29.3 ? . this adds to the two 85 ? series output elements to give a total load across the amplifier outputs of 170 ? + 29.3 ? = 199.3 ? . to test a particular adc interface rlc filter and converter input impedance, replace r11 and r12 with rf chip inductors, load c10 and c11 with the specified adc input capacitance and r26 with the specified adc differenti al input r. with these loaded, the remaining resistive elements (r24, r25, r13, r14) are set to hit a desired total parallel impedance to implement the desired filter (must be < than the adc inpu t differential r since that sits in parallel with any "external" elements) and achieve a 25 ? source looking into each side of the tap point transformer. this evm board includes a user's manual showing a number of example circuits and tested results. available on the intersil web site in the ISL55210 pr oduct information page. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL55210 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 2, 2011 fn7811.0 initial release
ISL55210 17 fn7811.0 march 2, 2011 figure 38. schematic for ISL55210, isl55211 single input transformer evm rev. c in out c2 100nf c4 100nf c5 100nf r3 50 ? r4 50 ? adt2-1t r6 0 ? c3 100nf r7 0 ? r5 200 ? r8 200 ? r15 50 ? r9 85 ? c6 1f c7 1f r10 85 ? fb+ 1 vi- 2 vi+ 3 fb- 4 gnd 5 vs+ 6 pd 7 gnd 8 vo- 9 nc 10 nc 11 vo+ 12 gnd 13 vcm 14 vs+ 15 gnd 16 u1 ISL55210, adt1-1wt r0 dnp r16 50 ? c8 1f r11 0 ? r12 0 ? r13 35.5 ? r14 35.5 ? r17 200 ? r20 200 ? /dnp r18 50 ? r21 200 ? /dnp c9 100nf r19 1k/dnp tp1 test point tp2 difprobe r22 50 ? pd c1 1f r2 dnp r1 dnp +vs gnd + c1001 4.7f l1 bead c1002 1.0f vcc r23 0 ? r24 0 ? r25 0 ? r26 dnp c11 dnp c10 dnp r27 0 ? r28 0 ? /dnp nc 1 a 2 gnd 3 y 4 vcc 5 74ahc1g04 cterm1 2.2pf cterm2 2.2pf isl55211
ISL55210 18 fn7811.0 march 2, 2011 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail ?x? jedec reference draw ing: mo-220 weed. 7.

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